This disclosure relates generally to integrated circuit semiconductor devices, and more particularly to memory devices.
Conventional silicon microelectronics typically use horizontally formed metal oxide semiconductor field effect transistors (MOSFET), in which the surface of a substrate on or in which the MOSFET is formed is oriented parallel to a gate oxide layer and parallel to a gate electrode arranged on the gate oxide layer. In order to achieve further miniaturization, vertically layered transistors have been formed in which the gate oxide layer is arranged essentially perpendicular to the surface of the substrate on or in which the vertical transistor is formed.
A vertical transistor has the advantage over planar technology in that the vertical transistor has a smaller area requirement in the plane of the substrate. In other words, with vertical transistors it is possible to achieve a higher integration density of transistors per substrate surface than with horizontal transistors. Using transistors of reduced dimension, switching elements with shortened switching times can be achieved since the length of the conductive channel can also be shortened.
One area of application for such transistors is memory devices, such as static random access memory (SRAM) devices and dynamic random access memory (DRAM) devices. DRAM memory cells are essentially made up of a capacitor, and data are stored in the DRAM memory cells in the form of electric charges that need to be periodically refreshed. SRAM memory cells store data using flip-flops, so an SRAM has faster access time as compared to a DRAM, and refreshing memory cells is not required with an SRAM.
A common SRAM memory cell configuration uses six transistors connected between an upper reference potential VDD and a lower reference potential VSS in such a way that one of two storage nodes can be occupied by the information to be stored, with the complementary information stored at the other storage node. In prior implementations, the transistors of the memory cell have been arranged in essentially parallel rows on a generally octagonal or rectangular base area of a substrate. However, such arrangements may not provide an optimum use of substrate area. It is desirable to further reduce the space requirement of an SRAM memory cell on or in a surface region of a substrate.
For these and other reasons, there is a need for the present invention.